AI/TLDR

FeSens · 2026-04-29 · notable

Auto-Architecture: An Autonomous Loop Optimizes a RISC-V CPU 92% in 9 Hours

A solo Show HN points Karpathy's autoresearch loop at SystemVerilog. An LLM proposes microarchitectural hypotheses for a 5-stage RV32IM core; a verifier runs formal checks, simulation and FPGA synthesis; only changes that improve CoreMark/MHz get merged.

auto-arch-tournament GitHub repository social preview

Karpathy's autoresearch idea, but the optimization target is a CPU's RTL instead of a neural net.

Key specs

GitHub stars38
Hypotheses tested73
Hypotheses accepted10
Wall clock duration9h 51m
Baseline iter/s301
Final iter/s577
Improvement92%
Vs vex riscv+56%
Final core mark/mhz2.91
Show hn points155

What is it?

An open experiment by FeSens that points a coding-agent research loop at a textbook 5-stage in-order RV32IM SystemVerilog core. The agent proposes microarchitectural hypotheses (forwarding tweaks, branch-predictor changes, pipeline tweaks) as YAML, schema-checked against a hypothesis schema, and only accepted ones become commits.

How does it work?

Each round, an LLM (Claude or Codex) drafts a hypothesis and an implementation in an isolated worktree. A verifier stack runs riscv-formal proofs, Verilator simulation, and yosys/nextpnr FPGA synthesis to check correctness, frequency and area. CoreMark iterations per second per MHz is the fitness signal. Hypotheses that pass formal verification AND raise CoreMark/MHz get merged; the rest are rejected.

Why does it matter?

Most autoresearch demos so far have stayed inside Python and gradient descent. This is a concrete public example of the same loop applied to RTL — a domain where the verifier is hard but exists. The author's takeaway, echoed across HN comments: the frontier isn't the loop, it's the verifier you can plug into it.

Who is it for?

hardware engineers experimenting with AI agents, autoresearch hobbyists, anyone curious how Karpathy's recipe generalizes outside ML.

Try it

git clone https://github.com/FeSens/auto-arch-tournament

Sources · 2 outlets

Tags

  • autoresearch
  • coding-agent
  • cpu-design
  • risc-v
  • systemverilog
  • fpga
  • verifier
  • show-hn
  • claude
  • codex
  • hardware

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